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| Example Overlap Test Result |
gnat Overview
Seed Solutions, Version 1.03
gnat, Greg's Network Analyzer Test program, is intended to provide a low-level interface to the N2PK VNA. The VNA is centered around two DDS (direct digital synthesis) chips, and a 24-bit ADC (analog to digital converter). gnat can be used to set the DDS (AD9851) state, and read the ADC (LTC2410) conversion output. I used gnat to help test my first VNA. gnat does not make any interesting electrical measurements, such as reflection coefficient or impedance.
Starting with version 1.03 of gnat, the LTC2440 ADC is supported. This includes the ability to change conversion rates. If you change the conversion rate, you should make sure that the Sleep Interval is not greater than the conversion time, unless you want the conversion to finish before gnat begins to wait for it.
Version 1.03 also begins support for multiple detectors, and multiple control signal mappings. The supported mappings are the extended N2PK parallel port assignments, and the OZ mapping, which uses external hardware to control the conversion rate of the LTC2410 ADC.
gnat gains access to the VNA through an API named VNAccess. This library provides a register-level interface to the DDS and ADC chips. All of the clocking and synchronization details are handled by VNAccess.
Frequencies are entered on the main dialog, and on the Options dialog (for the master oscillator). Frequency data is accepted and displayed in units of either kilohertz (KHz) or megahertz (MHz). The difference, of course, is the location of the decimal point.
Frequency values are limited to a maximum of 180 MHz. Frequency resolution is one-tenth Hz. While additional input digits will be accepted (on the right) without error, they will be ignored.
In the case of the KHz mode, an optional comma is allowed between the MHz and KHz digits.
Illegal input is rejected as it is entered, and the computer will issue an ear-shattering high-pitched beep. Ok, it will just meekly beep at you.
The ADC converter produces a result which is captured in a 32-bit register. That register, or a subset of that register, is recovered from the chip by VNAccess. gnat always obtains all 32 bits. A portion of that 32-bit register holds the 24-bit result. Other bits in the register are used to indicate out of range conditions on the input signal.
There are two different ADC data display formats. The first is as a voltage. The value has limits of -1.25 through +1.25 VDC, If the overflow indicators are present, the voltage reading will be replaced with either - OVF or + OVF, indicating a negative or positive out of range input voltage.
The second display format displays the raw data bits coming from the ADC. The display consists of three, space-separated fields. The left-most field is a single digit which contains the top 3-bits of the register. The next field is a 6-digit hex number, which is the standard 24-bit data result (unsigned 24-bit count). The final field is a 2-digit hex number containing the bottom 5 bits of register data.
The choice of ADC data display is made with a check box control on the Options dialog box.
Continuous ADC mode is selected on the Options dialog box. When checked, the ADC is run continuously, one sample after another. Each resultis displayed in the Result field, using the format specified on the Options dialog. The timing for each conversion is specified on the Options dialog box.
When continuous ADC mode is running, it will not be possible to enter Overlap Test mode, since both mode suggest continuous operation, and only one at a time is allowed.
NOTE: there is no synchronization between setting the DDS chips and making ADC readings on the main dialog window. Each activity is separate and unrelated. Only the Overlap Test mode synchronizes DDS setting and ADC reading.
The Overlap Test dialog can be used to start and stop the Overlap Test. This test sets the RF and LO DDS chips to the same frequency. The frequency is taken from the RF DDS frequency on the main dialog window. When the test is started, the LO DDS is cycled through all 32 phase shift combinations, over and over. Each ADC conversion will be made with the timing parameters specified on the Options dialog box.
When the test is started, the white plotting area is cleared. When a ADC conversion is complete, the data value is plotted, moving from left to right. The data is connected via straight line segments. When the plot reaches the right edge, the window will be cleared, and drawing will be restarted on the left side of the window.
In some cases, due to the pipelined nature of the Overlap Test, the very first reading after clicking Start Test may represent data from the last ADC conversion, started before the dialog was created. In other words, data unrelated to the current Overlap Test. If the trace is not continuous, simply wait until the second pass through the phase values, which will display data completely related to the current test.
The shape of the curve should be that of a sine wave, covering one complete cycle across the screen. In other words, the plot should flow seamlessly from the right edge back to the left edge. There is no particular phase synchronization between the wave and the window. There are cases where the amplitude will be very small, making the plot appear to be a straight horizontal line. An open detector, for example, will create that situation. For testing purposes, I connected the LO DDS output to the detector LO input, and the RF DDS output to the detector RF input. The following plot was created.
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| Example Overlap Test Result |
The sine wave signature utilizes both DDS chips and the ADC. While not a 100% coverage diagnostic of the board, it strongly suggests that the board is functional.
The performance number reported is a function of several factors. The first factor is the Setup Time, which is specified on the Options dialog. The is the time between changing the DDS chips, and starting the ADC conversion. This period is followed by the longer of either the actual ADC conversion time, or, the specified Sleep Interval, which is also specified on the Options dialog. A minor factor in the overall performance is the time that it takes to execute output instructions on the computer. At a minimum, approximately 150 output instructions are required to set the DDS chips, and read the ADC. The output instruction time is a function of the computer speed. For a fast computer, the total time spent communicating with the VNA is on the order of 0.15 ms. An old boat-anchor PC might take 0.5 ms for the same amount of work. While this overhead is very small, it does become more significant as the ADC conversion rate increases.
If you are interested in measuring the raw performance of the ADC, you should set the Setup Time and Sleep Interval to 0. This will isolate the ADC, and make it the sole factor, except for the parallel port communication overhead. The computer should also be otherwise idle, so that other programs are not competing for CPU cycles. Of course when using a VNA to make real measurements, the Setup Time must be set to a reasonable value, such as 10 ms.
Last update:
Sunday, October 17, 2004 06:34:51 PM
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